DM9102AT datasheet(47/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

16.1

SLEEP

0,RW

Sleep Mode:

Writing a 1 to this bit will cause PHY entering the Sleep mode and power

down all circuit except oscillator and clock generator circuit. When waking up

from Sleep mode (write this bit to 0), the configuration will go back to the state

before sleep; but the state machine will be reset

16.0

RLOUT

0,RW

Remote Loop out Control:

When this bit is set to 1, the received data will loop out to the transmit channel.

This is useful for bit error rate testing

DAVICOM Specified Configuration and Status Register (DSCSR) - 11h

Bit

Name

Default

Description

17.15

100FDX

1, RO

100M Full Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation 1 mode is a 100Mbps Full Duplex mode. The

software can read bit[15:12] to see which mode is selected after Auto-

negotiation. This bit is invalid when it is not in the Auto-negotiation mode.

17.14

100HDX

1, RO

100M Half Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation 1 mode is a 100Mbps Half Duplex mode. The

software can read bit[15:12] to see which mode is selected after Auto-

negotiation. This bit is invalid when it is not in the Auto-negotiation mode.

17.13

10FDX

1, RO

10M Full Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation 1 mode is a 10Mbps Full Duplex mode. The

software can read bit[15:12] to see which mode is selected after Auto-

negotiation. This bit is invalid when it is not in the Auto-negotiation mode.

17.12

10HDX

1, RO

10M Half Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation 1 mode is a 10Mbps Half Duplex mode. The

software can read bit[15:12] to see which mode is selected after Auto-

negotiation. This bit is invalid when it is not in the Auto-negotiation mode.

17.11-17.9

Reserved

000, RW

Reserved:

Write as 0, ignore on read

17.8-17.4

PHYAD[4:0]

00001, RW PHY Address Bit 4:0:

The first PHY address bit transmitted or received is the MSB of the address

(bit 4). A station management entity connected to multiple PHY entities must

know the appropriate address of each PHY. A PHY address of <00000> will

cause the isolate bit of the BMCR (bit 10, Register Address 00) to be set.

17.3-17.0

ANMB[3:0]

0000, RO Auto-negotiation Monitor Bits:

These bits are for debug only. The Auto-negotiation status will be written to

these bits.

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