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DM9102AT Datasheet(PDF) 72 Page - List of Unclassifed Manufacturers |
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DM9102AT Datasheet(HTML) 72 Page - List of Unclassifed Manufacturers |
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72 / 77 page  DM9102A Single Chip Fast Ethernet NIC controller 72 Final Version: DM9102A-DS-F03 August 28, 2000 Direct Mode Boot ROM Timing Frame# Irdy# Trdy# Devsel# CBEL[3:0] AD[31:0] MD[7:0] MA[17:0] ROMCS tCBAD t1ADL t2ADL t3ADL t4ADL tADTD tRC Symbol Parameter Min. Typ. Max. Unit Conditions tRC Read Cycle Time - 50 - PCI clock - tCBAD Bus Command to first address delay - 18 - PCI clock - t1ADL first address length - 8 - PCI clock - t2ADL second address delay - 8 - PCI clock - t3ADL third address delay - 8 - PCI clock - t4ADL fourth address delay - 7 - PCI clock - tADTD end of address to Tardy active - 1 - PCI clock - EEPROM Timing ROMCS EECK EEDO tCSKD tECKC tEDSP tECSC Symbol Parameter Min. Typ. Max. Unit Conditions tECKC Serial ROM clock EECK period 64 - - PCI clock - tECSC Read Cycle Time 1792 - - PCI clock - tCSKD Delay from ROMCS High to EECK High 28 - - PCI clock - tEDSP Setup Time of EEDO to EECK 24 - - PCI clock - |
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