DM9102AT datasheet(17/77 Pages) ETC

17 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

and bit 6 are set.

Address/Data Stepping (0 For No Stepping)

Parity Error Response Enable/Disable

Setting this bit will enable the DM9102A to assert PERR# on the detection

of a data parity error and to assert SERR# for reporting address parity

error.

VGA Palette Snooping (0 For Not Support)

Memory Write and Invalid (0 For Not Implementation)

The DM9102A only generates Memory write cycle.

Special Cycles (0 For Not Implementation)

Master Device Capability Enable/Disable

When this bit is set, DM9102A has the ability of master mode operation.

Memory Space Access Enable/Disable

This bit controls the ability of memory space access. The memory access

includes memory mapped I/O access and Boot ROM access. As the

system boots up, this bit will be enabled by BIOS for Boot ROM memory

access. While in normal operation using memory mapped I/O access, this

bit should be set by driver before memory access cycles.

I/O Space Access Enable/Disable

This bit controls the ability of I/O space access. It will be set by BIOS after

power on.

Revision ID (xxxxxx08 - PCIRV)

Revision ID

Class Code

Revision Major Number

Revision Minor Number

Bit

Default

Type

Description

31:8

020000h

Class Code (020000h)

This is the standard code for Ethernet LAN controller.

7:4

0011

Revision Major Number

This is the silicon-major revision number that will increase for the subsequent

versions of the DM9102.A.

3:0

0001

Revision Minor Number

This is the silicon-minor revision number that will increase for the subsequent

versions of the DM9102A.

DM9102AT Datasheet(PDF) 17 Page - List of Unclassifed Manufacturers

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