DM9102AT datasheet(7/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Pin Description

I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power,

LI = reset Latch Input, # = asserted Low

PCI Bus and CardBus Interface Signals

Pin No.

128QFP/128TQFP

Pin Name

I/O

Description

113

INT#

O/D

Interrupt Request

This signal will be asserted low when an interrupt condition

as defined in CR5 is set, and the corresponding mask bit in

CR7 is not set.

114

RST#

System Reset

When this signal is asserted low, DM9102A performs the

internal system reset to its initial state.

115

PCICLK

PCI system clock

PCI bus clock that provides timing for DM9102A related to

PCI bus transactions. The clock frequency range is up to

40MHz.

117

GNT#

Bus Grant

This signal is asserted low to indicate that DM9102A has

been granted ownership of the bus by the central arbiter.

118

REQ#

Bus Request

The DM9102A will assert this signal low to request the

ownership of the bus.

119

PME#

O/D

Power ManagementEvent.

Open drain. Active Low. The DM9102A drive it low to

indicates that a power management event has occurred.

IDSEL

Initialization Device Select

This signal is asserted high during the Configuration Space

read/write access.

FRAME#

I/O

Cycle Frame

This signal is driven low by the DM9102A master mode to

indicate the beginning and duration of a bus transaction.

IRDY#

I/O

Initiator Ready

This signal is driven low when the master is ready to

complete the current data phase of the transaction. A data

phase is completed on any clock both IRDY# and TRDY#

are sampled asserted.

TRDY#

I/O

Target Ready

This signal is driven low when the target is ready to complete

the current data phase of the transaction. During a read, it

indicates that valid data is asserted. During a write, it

indicates the target is prepared to accept data.

DEVSEL#

I/O

Device Select

The DM9102A asserts the signal low when it recognizes its

target address after FRAME# is asserted. As a bus master,

the DM9102A will sample this signal that insures its

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