DM9102AT datasheet(29/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Close descriptor by clearing owner bit of descriptor

Close descriptor by writing status

Receive process suspended due to buffer unavailable

Purge the current frame from the receive FIFO

because of unavailable receive buffer

NIS

0,RW

Normal Interrupt Summary

Normal interrupt includes any of the three conditions :

CR5<0> – TXCI : Transmit Complete Interrupt

CR5<2> – TXDU : Transmit Buffer Unavailable

CR5<6> – RXCI : Receive Complete Interrupt

AIS

0,RW

Abnormal Interrupt Summary

Abnormal interrupt includes any interrupt condition as shown below excluding Normal

Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7),

RXPS(bit8), RXWT(bit9), TXER(bit10), GPT(bit11), SBE(bit13).

ERI

0,RW

Early Receive Interrupt

This bit will be set when early receive interrupt has happened.

SBE

0,RW

System Bus Error

The PCI system bus errors will set this bit. The type of system bus error is shown in

CR5<25:23>.

LCI

0,RW

Link Status Change Interrupt

This bit will be set when link status change.

GPT

0,RW

General-purpose Timer Expired

This bit is set to indicate the general-purpose timer (described in CR11) has expired.

TXER

0,RW

Transmit Early Interrupt

Transmit Early Interrupt is set when the full packet data has been moved from host

memory into transmit FIFO. It willinform the host to process next step before the

transmission end. Transmit complete event CR5<0> will clear this bit automatically.

RXWT

0,RW

Receive Watchdog Timer Expired

This bit is set to indicate receive watchdog timer has expired.

RXPS

0,RW

Receive Process Stopped

This bit is set to indicate receive process enters the stopped state.

RXDU

0,RW

Receive Buffer Unavailable

This bit is set when the DM9102A fetches the next receive descriptor that is still

owned by the host. Receive process will be suspended until a new frame enters or

the receive polling command is set.

RXCI

0,RW

Receive Complete Interrupt

This bit is set when a received frame is fully moved into host memory and receive

status has been written to descriptor. Receive process is still running and continues to

fetch next descriptor.

TXFU

0,RW

Transmit FIFO Underrun

This bit is set when transmit FIFO has underrun condition during the packet

transmission. It may happen due to the heavy load on bus, receive process

dominates in full-duplex operation, or transmit buffer unavailable before end of

packet. In this case, transmit process is placed in the suspend state and underrun

error TDES0<1> is set.

TXJT

0,RW

Transmit Jabber Timer Expired

This bit is set when the jabber timer expired with the transmitter is still active.

Transmit process will be aborted and placed in the stop state. It also causes transmit

jabber timeout TDES0<14> to assert.

TXDU

0,RW

Transmit Buffer Unavailable

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