CS43L36 datasheet(39/89 Pages) CIRRUS

39 / 89 page

DS1081F3

CS43L36

4.5 Audio Serial Port (ASP)

• If ASP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See Fig. 4-21.

• If ASP_STP = 1, the frame begins when LRCK/FSYNC transitions from low to high. See Fig. 4-22.

In 50/50 Mode, left and right channels are programmed independently to output when LRCK/FSYNC is high or low—that

is, the channel-active phase. The active phase is controlled by ASP_RXx_CHy_AP (see Section 7.14). If x_AP = 1, the

respective channel is output if LRCK/FSYNC is high. If x_AP = 0, the channel is output if LRCK/FSYNC is low.

Note: Active phase has no function if 50/50 Mode = 0 or ASP_RX1_2FS = 1.

In 50/50 Mode, the channel location (see Section 4.5.3) is calculated within the channel-active phase. If there are N bits

in a frame, the location of the last bit of each active phase is equal to (N/2) – 1.

4.5.6

Serial Port Status

Each serial port has sticky, write-1-to-clear status bits related to capture paths. These bits are described in Section 7.4.3.

Mask bits (Section 7.4.12) determine whether INT is asserted when a status bit is set. Table 4-9 provides an overview.

Figure 4-21. Example 50/50 Mode (ASP_STP = 0)

Figure 4-22. Example 50/50 Mode (ASP_STP = 1)

Table 4-9. Serial Port Status

Name

Direction

Description

Request

Overload

Set when too many input buffers request processing at the same time. If all channel

registers are properly configured, this error status should never be set.

ASPRX_OVLD p. 67

LRCK Error

Logical OR of LRCK Early and LRCK Late (see below).

ASPRX_ERROR p. 67

LRCK Early

Set when the number of SCLK periods per LRCK phase (high or low) is less than the

expected count as determined by x_LCPR and x_LCHI.

Note: The Rx LRCK early interrupt status is set during the first receive LRCK early event.

Subsequent receive LRCK early events are indicated only if valid LRCK transitions are

detected.

ASPRX_EARLY p. 67

LRCK Late

Set when the number of SCLK periods per LRCK phase (high or low) is greater than the

expected count as determined by x_LCPR and x_LCHI.

ASPRX_LATE p. 67

No LRCK

Note: Set when the number of SCLK periods counted exceeds twice the value of LRCK

period (x_LCPR) without an LRCK edge.

ASPRX_NOLRCK p. 67

LRCK

...

x_STP = 0

SCLK

...

Channel y

Channel z

Next Sample

Previous Sample

x_CHy_LOC = 0, x_CHy_AP = 0

x_CHz_LOC = 0, x_CHz_AP = 1

SDIN

Channel z

Channel y

Next Sample

Previous Sample

x_CHz_LOC = 0, x_CHz_AP = 0

x_CHy_LOC = 0, x_CHy_AP = 1

This diagram assumes x_FSD = 0

Channel location index

x_CHy_LOC, x_CHz_LOC)

N/2 – 1

N/2 – 2

N/2 – 3

...

N/2 – 1

N/2 – 2

N/2 – 3

...

LRCK

SCLK

...

Channel y

Channel z

Next Sample

Previous Sample

x_CHy_LOC = 0, x_CHy_AP = 1

x_CHz_LOC = 0, x_CHz_AP = 0

SDIN

Channel z

Channel y

Next Sample

Previous Sample

x_CHz_LOC = 0, x_CHz_AP = 1

x_CHy_LOC = 0, x_CHy_AP = 0

...

x_STP = 1

Channel location index (x_CHy_LOC, x_CHz_LOC)

N/2 – 1

N/2 – 2

N/2 – 3

...

N/2 – 1

N/2 – 2

N/2 – 3

...

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