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CS43L36 Datasheet(PDF) 34 Page - Cirrus Logic |
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CS43L36 Datasheet(HTML) 34 Page - Cirrus Logic |
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34 / 89 page  DS1081F3 34 CS43L36 4.5 Audio Serial Port (ASP) 4.4.3.4 Powering Down the PLL To power down the PLL, clear PLL_START. 4.5 Audio Serial Port (ASP) The CS43L36 has an ASP to communicate audio and voice data between system devices, such as application processors and Bluetooth® transceivers. ASP_SCLK_EN (see p. 65) must be set whenever DAI is used. The ASP can be configured to TDM, I2S, and left justified (LJ) audio interfaces. Note: A maximum of two input channels are supported in TDM Mode. 4.5.1 Slave Mode Timing The ASP can operate as a slave to another device’s timing, requiring ASP_SCLK and ASP_LRCK/FSYNC to be mastered by the external device. If ASP_HYBRID_MODE is cleared (see p. 65), the serial port acts as a slave. If ASP_HYBRID_ MODE is set, the port is in Hybrid-Master Mode (see Section 4.5.2). In Slave Mode, ASP_SCLK and ASP_LRCK are inputs. Although the CS43L36 does not generate interface timings in Slave Mode, the expected LRCK and SCLK format must be programmed as it is in Hybrid-Master Mode. Table 4-8 shows supported serial-port sample rate examples. Note that some rates require use of the PLL and/or SRC. 4.5.2 Hybrid-Master Mode Timing In Hybrid-Master Mode, ASP_LRCK is derived from ASP_SCLK; the ASP_SCLK/ASP_LRCK ratio must be N x FS, where N is a large enough integer to support the total number of bits per ASP_LRCK period for the audio stream to be transferred. In either 50/50 Mode or I2S/LJ Mode, the ASP_SCLK/ASP_LRCK ratio must be NE xFS, where NE is an even integer. The serial port generates an internal LRCK/FSYNC from an externally mastered ASP_SCLK, allowing single clock-source mastering to the CS43L36. In Hybrid-Master Mode, the serial port must provide a left-right/frame sync signal (ASP_LRCK/ FSYNC) given an externally generated bit clock (ASP_SCLK). Table 4-6 shows supported serial-port sample-rate examples. Other rates are possible, but the rules stipulated above must be met. Note that some rates require use of the PLL or SRC. Table 4-6. Supported Serial-Port Sample Rates SCLK Frequency (MHz) Serial Port Sample Rate (kHz) 8.0 11.025 11.029 12 16 22.05 22.059 24 32 44.1 44.118 48 88.2 88.235 96 176.4 176.471 192 1.4112 — x — — — x — — — x — — x — — x — — 2.8224 — x — — — x — — — x — — x — — x — — 5.6448 — x — — — x — — — x — — x — — x — — 11.2896 — x — — —x —— — x — — x — — x — — 22.5792 — x — — — x — — — x — — x — — x — — 1.024 x — — — x — — — x —— — — —— — — — 2.048 x — — — x — — — x —— — — —— — — — 4.096 x — — — x — — — x —— — — —— — — — 8.192 x — — — x — — — x —— — — —— — — — 2 x — — — x — — — — —— — — —— — — — 3x — x x — — x x — — x — — x — — x — 4 x — — — x — — — x —— — — —— — — — 6x — x x x — x x — — x x — x — — x — 12 x — x x x — x x x — x x — x x — x — 24 x — x x x — x x x — x x — x x — x x 1.536 x — — x x — — x x — — x — — x — — x 3.072 x — — x x — — x x — — x — — x — — x 6.144 x — — x x — — x x — — x — — x — — x 12.288 x — — x x — — x x — — x — — x — — x 24.576 x — — x x — — x x — — x — — x — — x 9.6 x — — x x — — x x — — x — — x — — x 19.2 x — — x x — — x x — — x — — x — — x |
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