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CS43L36 Datasheet(PDF) 9 Page - Cirrus Logic |
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CS43L36 Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 89 page ![]() DS1081F3 9 CS43L36 1.4 Electrostatic Discharge (ESD) Protection Circuitry VP/ GNDA GNDHS HS3 TSTO TSTI TSTI TSTO TSTO TSTI VP VL_SEL INT WAKE RESET DIGLDO_PDN +VCP_ FILT/ –VCP_ FILT +VCP_FILT –VCP_FILT FLYN HPSENSA HPSENSB HPOUTA HPOUTB GNDCP VP/ –VCP_ FILT FLYC FLYP HS3_REF TSTO TSTI TIP_SENSE 1.See Section 5.5 for additional information regarding VD_FILT andVL. Table 1-2. ESD Domains (Cont.) ESD Domain Signal Name (See * in Topology Figures for Pad) Topology Substrate (GNDA) GNDCP +VCP_FILT VP –VCP_FILT Substrate (GNDA) GNDHS VP/GNDA Domain VP/–VCP_FILT Domain +VCP_FILT/–VCP_FILT Domain * * * |
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