CS43L36 datasheet(45/89 Pages) CIRRUS

45 / 89 page

DS1081F3

CS43L36

4.10 Control-Port Operation

Control-port registers are accessed through the I2C interface, allowing the DAC to be configured for the desired

operational modes and formats.

4.10.1 I2C Control-Port Operation

The I2C control port can operate completely asynchronously with the audio sample rates. However, to avoid interference

problems, the I2C control port pins must remain static if no operation is required.

The control port uses the I2C interface, with the DAC acting as a slave device. The I2C control port can operate in the

following modes, which are configured through the I2C debounce register in Section 7.1.9:

• Standard Mode (SM), with a bit rate of up to 100 kbit/s

• Fast Mode (FM), with a bit rate of up to 400 kbit/s

• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s.

Note: ASP_SCLK is not required to be on when the control port is accessed, for state machines affected by register

settings to advance.

SDA is a bidirectional data line. Data is clocked into and out of the CS43L36 by the SCL clock. Fig. 4-26–Fig. 4-29 show

signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while the clock is high.

A Stop condition is defined as a rising transition of SDA while the clock is high. All other SDA transitions occur while the

clock is low.

The register address space is partitioned into 8-bit page spaces that each comprise up to 127 8-bit registers. Address 0x00

of each page is reserved as the page indicator, PAGE. Writing to address 0x00 of any page changes the page pointer to

the address written to address 0x00.

To initiate a write to a particular register in the map, the page address, 0x00, must be written following the chip address.

Subsequent accesses to register addresses are treated as offsets from the page address written in the initial transaction.

To change the page address, initiate a write to address 0x00. To determine which page is active, read address 0x00.

Figure 4-26. Control-Port Timing, I2C Write of Page Address

The first byte sent to the CS43L36 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a

read, low for a write) in the LSB. To communicate with the CS43L36, the chip address field must match 1_0010, followed

by the state of the AD1 and AD0 pins.

Note: Because AD0 and AD1 logic states are latched at POR, dynamic addressing is not supported.

If the operation is a write, the next byte is the memory address pointer (MAP); the 7 LSBs of the MAP byte select the

address of the register to be read or written to next. The MSB of the MAP byte, INCR, selects whether autoincrementing

is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.

Each byte is separated by an acknowledge (ACK) bit, which the CS43L36 outputs after each input byte is read and is input

to the CS43L36 from the microcontroller after each transmitted byte.

24 25 26 27

SCL

CHIP ADDRESS(WRITE)

MAP BYTE

DATA

START

STOP

ACK

SDA

16 17 18 19

10 11

13 14 15

SDA

Source

Master

Pullup

Slave

Master

Pullup

ACK

MAP Addr = 0

Slave

Addr = 10010

CS43L36 Datasheet(PDF) 45 Page - Cirrus Logic

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