CS43L36 datasheet(66/89 Pages) CIRRUS

66 / 89 page

DS1081F3

CS43L36

7.3 Clocking Registers

7.3.7

ASP Frame Configuration

Address 0x1208

R/W

76543210

—

ASP_STP

ASP_5050

ASP_FSD

Default

000100

Bits Name

Description

7:5

—

Reserved

4ASP_

STP

ASP start phase. Controls which LRCK/FSYNC phase starts a frame. See Section 4.5.5 for details.

0 The frame begins when LRCK/FSYNC transitions from high to low

1 (Default) The frame begins when LRCK/FSYNC transitions from low to high

3ASP_

5050

ASP LRCK fixed 50/50 duty cycle. Determines whether the duty cycle is fixed or programmable. See Section 4.5.5 for details.

0 (Default) Programmable duty cycle. Determined by FSYNC_PULSE_WIDTH_LB (see p. 64), FSYNC_PULSE_WIDTH_

UB, and FSYNC_PERIOD_xSB (see p. 65).

1 50/50 Mode. Fixed 50% duty cycle

2:0

ASP_

FSD

ASP frame-start delay. Determines the delay before the start of an ASP frame in ASP_SCLK periods. See Section 4.5.2.

000 (Default) 0 delay

001 0.5 delay

010 1.0 delay …

101 2.5 delay

110–111 Reserved

7.3.8

FS Rate Enable

Address 0x1209

R/W

65432

—

FS_EN

Default

0000000

Bits Name

Description

7:3

—

Reserved

2:0 FS_EN Fs rate enable. Provides enables for all internally generated Fs rates. 0 = disabled; 1 = enabled. Section 4.6 gives details.

FS_EN[0] Enable IASRC 96K and lower rates.

FS_EN[2] Enable IASRC 192, 176.4, and 176.471 K rates

00 (Default) All disabled

7.3.9

Input ASRC Clock Select

Address 0x120A

R/W

43210

—

CLK_IASRC_SEL

Default

00000

Bits

Name

Description

7:2

—

Reserved

1:0

CLK_IASRC_

SEL

Input ASRC clock select. Selects input ASRC MCLKINT frequency. See Section 4.6 for programming details.

00 (Default) 6 MHz

01 12 MHz

10 24 MHz

11 Reserved

7.3.10 PLL Divide Configuration 1

Address 0x120C

R/W

765

43210

—

PLL_REF_INV

SCLK_PREDIV

Default

000000

Bits

Name

Description

7:3

—

Reserved

PLL_REF_

INV

Invert PLL reference clock. See Table 4.4.3 for programming guidelines.

0 (Default) Normal

1Inverted

1:0

SCLK_

PREDIV

PLL reference divide select. See Table 4.4.3 for programming guidelines.

00 (Default) Divide by 1

01 Divide by 2

10 Divide by 4

11 Divide by 8

CS43L36 Datasheet(PDF) 66 Page - Cirrus Logic

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