CS43L36 datasheet(32/89 Pages) CIRRUS

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DS1081F3

CS43L36

4.4 Clocking Architecture

Powering up the PLL can be accomplished in several configurations. Table 4-4 shows example configurations; the

sequences in Section 4.4.3.1 and Section 4.4.3.2 can be used as models.

MCLKINT combinations not shown in Table 4-4 can be determined by Eq. 4-1:

The internal PLL output must be between ~150 and ~300 MHz. The PLL_DIVOUT value must be an even integer. To

maximize flexibility in sample-rate choice, MCLKINT must be nominally 12 or 24 MHz.

PLL_CAL_RATIO determines the operating point for the internal VCO. For most configurations, the default value gives

proper performance. However, to keep the VCO within range, some scenarios require PLL_CAL_RATIO to be set during

the PLL power-up sequence (see Section 4.4.3). Use Eq. 4-2 to calculate the proper VCO setting at PLL start-up:

The value of n in Eq. 4-2 is determined by the following:

• If the result is less than or equal to 151, by default, n equals 1.

• If the result is less than 151, use the result to determine the PLL_CAL_RATIO setting.

• If the result is greater than 151, select another divide factor of n configurations for SCLK (where n = 2,3, …). The result

must be between 50 and 151 (see the power-up sequence in Section 4.4.3.2). Use the same n value to multiply PLL_

DIVOUT during the power-up sequence; see Step 2 in Section 4.4.3.1. The functional value must be restored (Step 8).

The same is shown in both standard examples.

4.4.3.1 PLL Power-Up Sequence (Example: SCLK = 4.096 MHz and MCLKINT = 12.288 MHz)

In this example, SCLK = 4.096 MHz and MCLKINT = 12.288 MHz.

1. Set SCLK_PREDIV to Divide-by-1 Mode (0x00).

2. Set PLL_DIVOUT to Divide-by-16 Mode (0x10). This reflects a value of n = 1, because the PLL_CAL_RATIO

generated by Eq. 4-2 equals 96. See that the PLL_DIVOUT entry for this configuration in Table 4-4 used a

Divide-by-16 Mode (0x10).

3. Clear the three fractional factor registers, PLL_DIV_FRAC (see Section 7.5.2).

4. Set the integer factor, PLL_DIV_INT to 48 (0x30).

5. Set the PLL Mode multipliers, PLL_MODE to 11 to bypass both 500/512 and 1029/1024 factors (0x03).

6. Set the PLL_CAL_RATIO to 96 (0x60, see Section 7.5.5).

7. Turn on the PLL by setting PLL_START (see p. 71).

8. As part of a standard sequence, after at least 800

s, the PLL_DIVOUT value would need to restored to 16 (0x10),

which is unnecessary here because that value did not change.

0x39

0xAB 52B5

0x11

11.2896

111

0x3B

0x13 B13B

0x10

118

0x3B

0x13 B13B

0x10

12.288

121

1. If MCLK_SRC_SEL = 0, the PLL is bypassed and can be powered down by clearing PLL_START (see p. 71).

2. Refer to the register description for the decode.

3. The text following this table explains the use of PLL_DIVOUT, shown by the example configurations in Section 4.4.3.1 and Section 4.4.3.2.

4. The variable n represents the divide ratio. See Eq. 4-2.

Equation 4-1. Configuring SCLK, MCLKINT Configurations

MCLKINT =

SCLK

(PLL_DIV_INT + PLL_DIV_FRAC)

SCLK_PREDIV

(500/512 or 1029/1024 or 1)

PLL_DIVOUT

Equation 4-2. Calculating the PLL_CAL_RATIO

PLL_CAL_RATIO =

MCLKINT x 32 x SCLK_PREDIV

n xSCLK

Table 4-4. Common PLL Setting Examples (Cont.)

SCLK

(MHz)

MCLK_SRC_SEL

(see p. 64) 1

SCLK_PREDIV

(see p. 66) 2

PLL_DIV_INT

(see p. 72)

PLL_DIV_FRAC

(see p. 72) 2

PLL_MODE

(see p. 72)

PLL_DIVOUT

(see p. 72) 3

MCLKINT

(MHz)

PLL_CAL_RATIO

(see p. 72)

n [4]

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