CS43L36 datasheet(33/89 Pages) CIRRUS

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DS1081F3

CS43L36

4.4 Clocking Architecture

4.4.3.2 PLL Power-Up Sequence (Example: SCLK = 12 MHz and MCLKINT = 24MHz)

In this example, SCLK = 12 MHz and MCLKINT =24MHz.

1. Set SCLK_PREDIV to Divide-by-4 Mode (0x02).

2. Set PLL_DIVOUT to Divide-by-16 Mode (0x10). This reflects a value of n = 2, because the PLL_CAL_RATIO

generated by Eq. 4-2 was greater than 151. See that the PLL_DIVOUT entry for this configuration in Table 4-4

used a Divide-by-8 Mode (0x08).

3. Clear the three fractional factor registers, PLL_DIV_FRAC.

4. Set the integer factor, PLL_DIV_INT to 64 (0x40).

5. Set the PLL mode multipliers, PLL_MODE to 11 to bypass both 500/512 and 1029/1024 factors (0x03).

6. Set the PLL_CAL_RATIO to 128 (0x80).

7. Turn on the PLL by setting PLL_START.

8. After at least 800

s, the PLL_DIVOUT value must be restored from 16 to 8 (0x08).

4.4.3.3 Nonstandard PLL Setting (Example: SCLK = 19.2 MHz and MCLKINT = 12 MHz)

In this example, SCLK = 19.2 MHz and MCLKINT = 12 MHz. (Note that a power-up sequence similar to Section 4.4.3.2 is

required for this configuration due to n =1.)

• SCLK = 19.2 MHz = available reference clock.

•MCLKINT = 12 MHz = desired internal MCLK.

• SCLK_PREDIV = 11 = divide SCLK by 8 as reference to PLL.

• PLL_DIV_INT = 0x50 = multiply reference clock by 80, yielding PLL out = 192 MHz.

• PLL_DIV_FRAC = 0x00 0000 = fractional portion equal to zero.

• PLL_MODE = 11 = 500/512 and 1029/1024 multipliers are bypassed.

• PLL_DIVOUT = 0x10 = divide PLL out by 16 to achieve MCLKINT of 12 MHz.

Table 4-5 shows nonstandard PLL configurations.

As shown in Fig. 4-13, the input to the PLL is the ASP_SCLK input pin.

Table 4-5. Nonstandard PLL Settings

SCLK

(MHz)

MCLK_SRC_SEL

(see p. 64)

SCLK_PREDIV

(see p. 66)

PLL_DIV_INT

(see p. 72)

PLL_DIV_FRAC

(see p. 72)

PLL_MODE

(see p. 72)

PLL_DIVOUT

(see p. 72)

MCLKINT

(MHz)

PLL_CAL_RATIO

(see p. 72)

n [1]

9.6

0x6E

0x40 0000

0x18

11.2896

0x50

0x00 0000

0x10

0x50

0x00 0000

0x10

12.288

0x6E

0x400000

0x0C

22.5792

150

0x50

0x00 0000

0x08

0x50

0x00 0000

0x08

24.576

19.2

0x6E

0x40 0000

0x18

11.2896

150

0x50

0x00 0000

0x10

0x50

0x00 0000

0x10

12.288

0x6E

0x40 0000

0x0C

22.5792

150

0x50

0x00 0000

0x08

107

0x50

0x00 0000

0x08

24.576

109

1. The variable n represents the divide ratio. See Eq. 4-2.

Figure 4-13. Clocking Architecture

ASP_SCLK

Fractional-N

PLL

MCLKINT

(+1.8 V)

PLL_START

CS43L36 Datasheet(PDF) 33 Page - Cirrus Logic

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