CS43L36 datasheet(35/89 Pages) CIRRUS

35 / 89 page

DS1081F3

CS43L36

4.5 Audio Serial Port (ASP)

Fig. 4-14 and Fig. 4-15 show the serial-port clocking architectures.

Figure 4-14. ASP SCLK Architecture

Figure 4-15. ASP LRCK Architecture

As shown in Fig. 4-16, the LRCK period (FSYNC_PERIOD_LB and FSYNC_PERIOD_UB, see p. 65) controls the number

of SCLK periods per frame. This effectively sets the frame length and the number of SCLK periods per Fs. Frame length

may be programmed in single SCLK period multiples from 16 to 4096 SCLK:Fs. If ASP_HYBRID_MODE (see p. 65) is

set, the SCLK period multiples must be set to 2 * n * Fs, where n

 {8, 9, …, 2048}.

Figure 4-16. ASP LRCK Period, High Width

FSYNC_PULSE_WIDTH_LB and FSYNC_PULSE_WIDTH_UB (see p. 64) control the number of SCLK periods for which

the LRCK signal is held high during each frame. Like the LRCK period, the LRCK-high width is programmable in single

SCLK periods, from at least one period to at most the LRCK period minus one. That is, the LRCK-high width must be

shorter than the LRCK period.

As shown in Fig. 4-17, if 50/50 Mode is enabled (ASP_5050 = 1, see p. 66), the LRCK high duration must be programmed

to the LRCK period divided by two (rounded down to the nearest integer when the LRCK period is odd). When the serial

port is in 50/50 Mode, setting the LRCK high duration to a value other than half of the period causes erroneous operation.

CLK DIV

DIVSEL

OUT

SCLK

LRCK_GEN

SCLK in to DAI CLKGEN

ASP_SCLK

MCLKDIV

p. 64

ASP_SCPOL_IN_DAC p. 65

ASP_SCLK_EN = 1

(See p. 65)

LRCK in

ASP_LRCK/FSYNC

LR Generation

PER

OUT

From SCLK

5050

DELAY

ASP_LCPOL_OUT p. 65

FSYNC_PULSE_WIDTH_LB p. 64

FSYNC_PULSE_WIDTH_UB p. 64

FSYNC_PERIOD_LB p. 65,

FSYNC_PERIOD_UB p. 65

ASP_5050 p. 66

ASP_FSD p. 66

ASP_LCPOL_IN p. 65

ASP_HYBRID_MODE p. 65

SCLK

LRCK

Falling

Edge

Rising

Edge

FSYNC_PERIOD

FSYNC_PULSE_WIDTH

...

CS43L36 Datasheet(PDF) 35 Page - Cirrus Logic

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