CS43L36 datasheet(7/89 Pages) CIRRUS

7 / 89 page

DS1081F3

CS43L36

1.4 Electrostatic Discharge (ESD) Protection Circuitry

Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the

substrate (GNDA) and the interrelations between some domains. Note that this figure represents the structure for the

internal protection devices and that additional protections can be implemented as part of the integration into the board.

Figure 1-3. Composite ESD Topology

N/A

I High Voltage Interface Supply. Power supply for

high voltage interface.

——

—

GNDA

N/A

I Analog Ground. Ground reference for the internal

analog section.

——

—

GNDL

N/A

I Digital Ground. Ground reference for interface

section.

——

—

GNDHS

N/A

I Headset Ground. Ground reference for the internal

analog section.

——

—

GNDCP

N/A

I Charge Pump Ground. Ground reference for the

internal HP amplifiers charge pump.

——

—

GNDD

N/A

I Digital Ground. Ground reference for the internal

digital circuits.

——

—

TSTI

N/A

I Test input. Connect to GNDD

—

TSTI

I Test input. Connect to GNDD.

—

TSTI

D1, E1,

E2, F1,

F2, G3

—

I Test input. Connect to GNDA.

—

TSTI

—

I Test input. Connect to GNDA.

—

TSTO

A4, A6 33,37

O Test output. No connection

—

TSTO

E3, F3,

18,19,

O Test output. No connection

—

1.There are no internal connections for the CS43L36.

2.The power supply is determined by ADPTPWR setting (see Section 7.10.1). VP is used if ADPTPWR = 001 (VP_CP Mode) or when necessary for

ADPTPWR = 111 (Adapt-to-Signal Mode).

ESD-sensitive device. The CS43L36 is manufactured on a CMOS process. Therefore, it is generically

susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while

handling and storing this device. This device is qualified to current JEDEC ESD standards.

Table 1-1. Pin Descriptions (Cont.)

Pin Name

CSP

Pin #

QFN

Pin #

Power

Supply

I/O

Pin Description

Internal

Connection1

Driver

Receiver

State at

Reset

Ground

Test

GNDL

Substrate

(GNDA)

VCP

GNDA

Substrate

(GNDA)

GNDCP

+VCP_FILT

–VCP_FILT

GNDHS

____________________

VL/GNDA Domain

____________________

VA/GNDA Domain

__________

VCP/GNDA

Domain

VP/GNDA Domain

_______________

VD_FILT/GNDA

Domain

VP/–VCP_FILT Domain

–VCP_FILT/+VCP_FILT Domain

GNDD

VD_FILT

Note: The asterisks indicate the pads with which the individual

pins from the corresponding domains are associated. These

pins are listed in Table 1-2.

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