CS43L36 datasheet(67/89 Pages) CIRRUS

67 / 89 page

DS1081F3

CS43L36

7.4 Interrupt Registers

7.4.1

Channel Overflow Interrupt Status

Address 0x1302

R/O

—

CHA_OVFL

CHB_OVFL

Default

Bits

Name

Description

7:2

—

Reserved

CHA_

OVFL

Channel overflow. Indicates the overrange status in the corresponding signal path. Rising-edge state transitions may cause

an interrupt, depending on the programming of the associated interrupt mask bit.

0 No digital clipping has occurred in the data path of the respective signal source.

1 Digital clipping has occurred in the data path of the respective signal source.

CHB_

OVFL

7.4.2

SRC Interrupt Status

Address 0x1303

R/O

76543210

—

SRC_IUNLK

—

SRC_ILK

Default

0000

xxxx

Bits

Name

Description

7:3

—

Reserved

SRC_IUNLK SRC unlock status. Indicates SRC unlock status for the input path. Status is valid only if serial-port LRCK is toggling.

0 Locked

1 Unlocked

1—

Reserved

SRC_ILK

SRC lock status. Indicates SRC lock status for the ASP input path. Status is valid only if serial-port LRCK is toggling.

0 Unlocked

1 Locked

7.4.3

ASP RX Interrupt Status

Address 0x1304

R/O

—

ASPRX_OVLD ASPRX_ERROR ASPRX_LATE ASPRX_EARLY ASPRX_NOLRCK

Default

Bits

Name

Description

7:5

—

Reserved

4ASPRX_

OVLD

ASP RX request overload. Set when too many input buffers request processing at once. 0No interrupt

1 Interrupt detected. ASP RX cannot retrieve data from the internal input buffers because at least one of the following

violations has occurred:

—The ASP RX core clock frequency is less than SCLK/8.

—The LRCK frame (non-50/50 Mode) or LRCK subframe (50/50 Mode) period is less than 16 SCLK periods (assuming

the ASP RX core clock frequency is equal to SCLK/8).

3ASPRX_

ERROR

ASP RX LRCK error. Logical OR of ASPRX_LATE and ASPRX_EARLY, described below.

0 No interrupt

1 Interrupt detected

2ASPRX_

LATE

ASP RX LRCK late. Determines whether the number of SCLK periods per LRCK phase (high or low) is greater than the

expected count, as determined by the FSYNC_PERIOD_xSB and FSYNC_PULSE_WIDTH_x fields.

0 No interrupt

1 Interrupt detected

1ASPRX_

EARLY

ASP RX LRCK early. Determines whether the number of SCLK periods per LRCK phase (high or low) is less than the expected

count, as determined by FSYNC_PERIOD_xSB (see p. 65) and FSYNC_PULSE_WIDTH_x (see p. 64).

0 No interrupt

1 Interrupt detected

0ASPRX_

NOLRCK

ASP RX no LRCK. Determines whether the SCLK periods counted exceeds twice the value of LRCK period (FSYNC_

PERIOD_xSB) without an LRCK edge.

0 No interrupt

1 Interrupt detected

CS43L36 Datasheet(PDF) 67 Page - Cirrus Logic

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