SPSB0813 datasheet(45/135 Pages) STMICROELECTRONICS

45 / 135 page

4.2.2.4

Data-in payload

The Payload (data byte 1 to data byte 3) is the data transferred to the device with every SPI communication. The

Payload always follows the OpCode and the address bits.

For write access the Payload represents the new data written to the addressed register. For read & clear

operations the Payload defines which bits of the addressed status register is cleared. In case of a ‘1’ at the

corresponding bit position the bit will be cleared.

For a read operation, the Payload is not used. For functional safety reasons it is recommended to set unused

Payload to ‘0’.

4.2.2.5

SDO frame

The data-out frame consists of 32 bits (GSB + data byte 1 to 3).

The first eight transmitted bits contain device related status information and are latched into the shift register at

the time of the communication start. These 8 bits are transmitted at every SPI transaction.

The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK

edge.

This could lead to an inconsistency of data between the GSB and Payload due to different shift register load

times. Anyhow, no unwanted status register clear should appear, as status information should just be cleared with

a dedicated bit clear after.

Figure 29. SDO frame

4.2.2.6

Global status byte (GSB)

The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the status registers. Therefore, no

direct read & clear can be performed on these bits inside the GSB.

Table 14. Global status byte

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

Bit 24

GSBN

RSTB

SPIE

PLE

Global status bit not (GSBN)

The GSBN is a logically NOR combination of bit 24 to bit 30. This bit can also be used as global status flag

without starting a complete communication frame as it is present directly after pulling CSN low.

Reset bit (RSTB)

The RSTB indicates a device reset. In case this bit is set, specific internal control registers are set to default and

kept in that state until the bit is cleared.

SPSB081

Signal description

DS14048 - Rev 1

page 45/135

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