SPSB0813 datasheet(42/135 Pages) STMICROELECTRONICS

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4.1.1

Physical layer

Figure 26. SPI pin description

4.2

Signal description

Chip select not (CSN)

The communication interface is de-selected, when this input signal is logically high. A falling edge on CSN

enables and starts the communication while a rising edge finishes the communication and the sent command is

executed when a valid frame was sent. During communication starts and stops the serial clock (SCK) has to be

logically low. The serial data out (SDO) is in high impedance when CSN is high or a communication timeout was

detected.

Serial clock (SCK)

This SCK provides the clock of the SPI. Data present at serial data input (SDI) is latched on the rising edge of

serial clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are

shifted out to serial data out (SDO).

Serial data input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising edge of serial clock (SCK).

Serial data output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial

clock (SCK).

4.2.1

Clock and data characteristics

The ST-SPI can be driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0

CPHA = 0

SPSB081

Signal description

DS14048 - Rev 1

page 42/135

SPSB0813 Datasheet(PDF) 42 Page - STMicroelectronics