C5C5EDELTA-RMSLASHD datasheet(41/114 Pages) NXP

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Pin Descriptions Grouped by Function

SONET OC-12 Transceiver Interface Configuration

SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a

CP within a cluster spends half its time performing receive functions, and the other half

performing transmit functions. Table 14 shows a CP Cluster configured for one OC-12

interface.

Table 14 OC-12 Signals Example

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 7

LVTTL

TCLK

Deskewed Transmit Clock (77.76MHz). This clock is used to

synchronize the transmit data.

CPn_1

Table 7

LVTTL

TCLKI

Transceiver Transmit Clock. This clock sets the frequency of the

transmit data and is typically sourced by the PHY chip.

CPn_2

Table 7

LVTTL

TXD(0)

Transmit Data (byte-wide data, least significant bit)

CPn_3

Table 7

LVTTL

OPU

TXD(1)

Transmit Data

CPn_4

Table 7

LVTTL

TXD(2)

Transmit Data

CPn_5

Table 7

LVTTL

TXD(3)

Transmit Data

CPn_6

Table 7

LVTTL

OPU

00F

Out of Frame

CPn+1_0

Table 7

CPn+1_1

Table 7

CPn+1_2

Table 7

LVTTL

OPD

TXD(4)

Transmit Data

CPn+1_3

Table 7

LVTTL

TXD(5)

Transmit Data

CPn+1_4

Table 7

LVTTL

TXD(6)

Transmit Data

CPn+1_5

Table 7

LVTTL

OPU

TXD(7)

Transmit Data (byte-wide data, most significant bit)

CPn+1_6

Table 7

CPn+2_0

Table 7

CPn+2_1

Table 7

LVTTL

IPU

RCLK

Receive Clock (77.76MHz)

CPn+2_2

Table 7

LVTTL

RXD(0)

Receive Data (byte-wide receive data, least significant bit)

CPn+2_3

Table 7

LVTTL

RXD(1)

Receive Data

CPn+2_4

Table 7

LVTTL

IPD

RXD(2)

Receive Data

CPn+2_5

Table 7

LVTTL

RXD(3)

Receive Data

CPn+2_6

Table 7

LVTTL

Frame Synchronization Pulse. This is valid during the third A2 of

the receive SONET frame.

CPn+3_0

Table 7

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D Datasheet(PDF) 41 Page - NXP Semiconductors

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