 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
C5C5EDELTA-RM/D Datasheet(PDF) 90 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
C5C5EDELTA-RM/D Datasheet(HTML) 90 Page - NXP Semiconductors |
|
|
90 / 114 page  90 CHAPTER 3: ELECTRICAL SPECIFICATIONS C3EN Low Speed Serial Interface Timing Specifications The low speed serial interface timing is shown in Figure 21 and described in Table 46. Figure 21 Low Speed Serial Interface Timing Diagram Cycle 2 Cycle 3 Tslc Tslss Tslhd Tslsd Tslhs SICL SIDA Tslst Tslb Table 46 Low Speed Serial Interface Timing Description SYMBOL PARAMETER MIN MAX UNIT Tslc SICL Cycle Time 2500 ns Tslss Set-up Time for Repeated START Condition 600 ns Tslhs Hold Time START Condition 600 ns Tslsd Data Set-up Time 250 ns Tslhd Data Hold Time 0.0 ns Tslst Set-up Time for STOP Condition 600 ns Tslb Bus Free Time Between a STOP and START Condition 1250 ns Cmax Capacitive load for each line of the bus 400 pF Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
