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C5C5EDELTA-RM/D Datasheet(PDF) 86 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 86 Page - NXP Semiconductors |
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86 / 114 page  86 CHAPTER 3: ELECTRICAL SPECIFICATIONS C3EN OC-12 Timing Specifications The OC-12 interface timing is shown in Figure 18 and described in Table 43. Figure 18 OC-12 Timing Diagram CPn_1 (TCLKI) Cycle 1 Cycle 1 Cycle 2 Cycle 3 Cycle 3 Cycle 4 Cycle 5 CPn_0 (TCLK) CPn+1_2-5 (Tx) CPn_1 (RCLK) CPn+2_2-6 (Rx) CPn+3_2-5 (Rx) Tc12i Tc12t Tc12r Tc12o Tc12s Tc12h Cycle 2 Tc12d Table 43 OC-12 Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tc12i OC-12 Transmit Cycle Time* * Input from PHY 12.86 ns Tc12d OC-3 Clock Duty Cycle 40 60 % Tc12t OC-12 Transmit Cycle Time† † Output from C-3e NP 12.86 ns Tc12o OC-12 Output Time‡ ‡ Aligned to TCLK 3.0 10.0 ns Tc12r OC-12 Receive Cycle Time 12.0 12.86 ns Tc12s OC-12 Setup Time 2.0 ns Tc12h OC-12 Hold Time 0.0 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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