C5C5EDELTA-RMSLASHD datasheet(45/114 Pages) NXP

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Pin Descriptions Grouped by Function

PROM Interface Signals

The PROM interface is a low speed I/O port that allows the C-3e NP to communicate

through external logic to PROM. The PROM clock is 1/

2 to

16 the core clock rate.The

maximum PROM size addressable is 4MBytes, and must use a “by 16” part. The PROM

signals are listed in Table 17.

Figure 5 shows the connections between the PROM Interface and external board logic.

The application is required to provide an external shift register with parallel-in and

parallel-out capabilities, and a parallel load register. Both devices should be

positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When

SPLD is deasserted the shift register shifts.

Table 17 PROM Interface Signals

SIGNAL

NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

SPDO

LVTTL

Serial Data Out

SPDI

LVTTL

Serial Data In

SPLD

LVTTL

When load is asserted on a positive clock

edge, the external logic performs a parallel

load. On each positive clock edge when

load is de-asserted, the shift registers shift.

When the PROM interface is idle:

• if SPLD is asserted HI it indicates low

speed serial protocol,

• if asserted LOW it indicates MDIO serial

protocol.

SPCK

LVTTL

Clock

TOTAL PINS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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