 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
C5C5EDELTA-RM/D Datasheet(PDF) 98 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
C5C5EDELTA-RM/D Datasheet(HTML) 98 Page - NXP Semiconductors |
|
|
98 / 114 page  98 CHAPTER 3: ELECTRICAL SPECIFICATIONS C3EN QMU SRAM (Internal Mode) Timing Specifications The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and described in Table 53. Figure 26 QMU SRAM (Internal Mode) Timing Diagram QACLKI Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Q_ctl QAn QDn (output) QDn (input) Tqc Tqdo Tqco Tqao Tqdv Tqds Tqdz Tqdh Table 53 QMU SRAM (Internal Mode) Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tqc QMU Cycle Time 6.7 ns Tqco QMU Ctrl Output 0.8 4.4 ns Loading is 50 Ω transmission line. Tqao QMU Addr Output 0.8 4.4 ns Loading is 50 Ω transmission line. Tqds QMU Data Setup 0.8 ns Tqdh QMU Data Hold 0.8 ns Tqdo QMU Data Output 0.9 4.4 ns Loading is 50 Ω transmission line. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
