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C5C5EDELTA-RM/D Datasheet(PDF) 99 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 99 Page - NXP Semiconductors |
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99 / 114 page ![]() AC Timing Specifications 99 03 Tqdz QMU Data Clk to Tri* 0.9 4.4 ns Tqdv QMU Data Clk to Driven* 0.9 4.4 ns * Not fully tested, values based on design/characterization. Table 54 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams SIGNAL GROUP INCLUDED SIGNALS Control (Q_ctl) QWEX Address (QAn) QA0-QA16 Data (QDn) QD0-QD31, QDPL, QDPH Table 53 QMU SRAM (Internal Mode) Timing Description (continued) SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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