C5C5EDELTA-RMSLASHD datasheet(52/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

C3EN

MRASX

A23

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered. MCSX

is considered part of the command code.

MWEX

A22

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered. MCSX

is considered part of the command code.

MCSX

A25

LVTTL

Chip Select: MCSX enables (registered LOW) and

disables (registered HIGH) the command decoder.

All commands are masked when MCSX is

registered HIGH. MCSX provides the external bank

selection on systems with multiple banks. MCSX is

considered part of the command code.

MDQM

MDQML

A20

A21

LVTTL

Input/Output Mask: MDQM is an input mask

signal for write accesses and an output enable

signal for read accesses. Input data is masked

when MDQM is sampled HIGH during a WRITE

cycle. The output buffers are placed in a high Z

state (two-clock latency) when MDQM is sampled

HIGH during the READ cycle.

NOTE: MDQML is an identical copy of MDQM

used to drive the loading on SDRAM

configurations with 2 DQM pins.

MDCLK

A26

LVTTL

IPD

Clock: MDCLK is driven by the system clock. All

SDRAM input signals are sampled on the positive

edge of the MDCLK. MDCLK also increments the

internal burst counter and controls the output

registers.

TOTAL PINS

160

Table 22 BMU SDRAM Interface Signals (continued)

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D Datasheet(PDF) 52 Page - NXP Semiconductors

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