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STE2004S Datasheet(PDF) 16 Page - STMicroelectronics |
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STE2004S Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 79 page ![]() Circuit description STE2004S 16/79 Figure 10. Automatic data RAM writing sequence with V=0 and data RAM mirrored format (MX=1)(a) Figure 11. Automatic data RAM writing sequence with V=1 and data RAM mirrored format (MX=1)(a) Figure 12. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=0) 321 0 98 99 100 101 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 LR0051 10 32 98 99 100 101 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 LR0052 BANK 0 BANK 1 BANK 2 Y CARR BANK 7 BANK 8 0123 98 99 100 101 X CARR LR0053 |
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