STE2004S datasheet(42/79 Pages) STMICROELECTRONICS

Part #	STE2004S

Description	102 x 65 single-chip LCD controller/driver

PDF	79 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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42 / 79 page

Bus interfaces

STE2004S

42/79

Figure 48.

68000-series parallel interface protocol in reading mode (several bytes)

4.3.2

8080-series parallel interface

If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or

transmit data. While CS pin is high the 8080 parallel interface is kept in reset.

Write mode

Data are latched on WR rising edge.

Read mode

Data is output on the D0-D7 bus on the RD rising edge. The data bus is set in high impedance

mode when RD is set to logic 1.

The I2C address or status byte is output on D0-D7 bus, accordingly to R bit value.

Figure 49.

8080-series parallel bus protocol - one byte transmission

D/C

R/W

LR0046

Note 1) Data Bus is configured in high impedence mode after evry RD rising edge

2) Always the same data is output on D0-D7

D/C

LR0083

STE2004S Datasheet(PDF) 42 Page - STMicroelectronics