68HC05CL48 datasheet(38/145 Pages) MOTOROLA

38 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

INTERRUPTS

MC68HC05CL48

4-6

REV 2.0

4.3.2 External Interrupts (IRQ0, IRQ1, IRQ2, KBI[3:7])

4.3.2.1

IRQ0, IRQ1, IRQ2

IRQ0, IRQ1, IRQ2 interrupt function is associated with PTA[0:2]. IRQ[0:2]

interrupts behave similar to IRQ except these are edge-triggered only. IRQ0 and

IRQ1 are both negative-edge triggered only and IRQ2 can be triggered on both

rising and falling edges. To enable this function, IRQE0, IRQE1 and IRQE2 bit of

the external interrupt control register (EXICR $1D) should be set ﬁrst. When an

appropriate edge occurring at the IRQ0, IRQ1 or IRQ2 pin and the interrupt mask

bit of the condition code register is cleared will cause an external interrupt to

occur. If the MCU has ﬁnished with the service routine, but the external interrupt

pin has not resumed backed to high, no further interrupt will be generated. If the

appropriate triggering edge occurs when the interrupt mask bit is set, the interrupt

signal will be latched, and interrupt will occur as soon as the interrupt mask bit is

cleared. The latch for IRQ0, IRQ1 and IRQ2 are cleared by reset or cleared by

writing a ‘0’ to the IRQF0, IRQF1 and IRQF2 bit in the external interrupt status

The interrupt service routine is speciﬁed by the contents of the memory locations

$FFF2 and $FFF3.

To prevent unwanted interrupts generated on RQ0, IRQ1 pins. A logic ‘1’ should

be written to these pins before setting their corresponding interrupt enable bits.

Likewise, A logic ‘1’ should be written to IRQ2 pin prior to setting the IRQ2

interrupt enable bit.

4.3.2.2

Keyboard Interrupts

Keyboard Interrupt function is associated with PTA[3:7]. The keyboard interrupt

function is enabled by setting the individual interrupt enable bits KBE[3:7]

(bits[3:7] of EXICR at $001D). When the KBE bit is set, the corresponding Port A

pin will be conﬁgured as an input pin, regardless of the DDR setting, and a 100k

ohm pull-up resistor is connected to the pin, as shown in Figure 4-3. When a high

to low transition is sensed on the pin, a keyboard interrupt will be generated,

provided the I-bit in the CCR is cleared.

The interrupt signal is latched, and it should be cleared by writing a ‘0’ to the

corresponding KBIF bit in the external interrupt status register ($1E EXISR) in the

interrupt service routine. This should be cleared after the key is debounced, or

unwanted keyboard interrupt signal will be generated.

The Keyboard Interrupt is negative-edge sensitive only, and the interrupt service

routine is speciﬁed by the contents of the memory locations $FFF2 and $FFF3.

68HC05CL48 Datasheet(PDF) 38 Page - Motorola, Inc

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