68HC05CL48 datasheet(43/145 Pages) MOTOROLA

43 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

RESETS

MOTOROLA

REV 2.0

5-1

SECTION 5

RESETS

The MCU can be reset in three ways:

•

by the initial power-on reset function, (POR)

•

by an active low input to the RESET pin, (RESET)

•

by a COP watchdog timer reset, (COPR)

5.1

EXTERNAL RESET (RESET)

The RESET pin is the only external source of a reset. This pin is connected to a

Schmitt trigger input gate to provide an upper and lower threshold voltage

separated by a minimum amount of hysteresis. This external reset occurs

whenever the RESET pin is pulled below the lower threshold and remains in reset

until the RESET pin rises above the upper threshold. This active low input will

generate the RST signal and reset the CPU and peripherals. Termination of the

external RESET input can alter the operating mode of the MCU.

The RESET pin can also be pulled to a low state by an internal pulldown that is

activated by the internal COP Watchdog or Power-on resets. This RESET pin

pulldown device will only be activated for one cycle of the internal clock, PH2,

when a COP Watchdog reset occurs; or will remain activated as long as counting

the power-on reset cycles or the low voltage is detected.

5.2

POWER-ON RESET (POR)

The internal POR is generated on power-up to allow the clock oscillator to

stabilize. The POR is strictly for power turn-on conditions and is not able to detect

a drop in the power supply voltage (brown-out). There is an oscillator stabilization

delay of 488 internal processor bus clock cycles (PH2) after the oscillator

becomes active. The RESET pin will be pulled down internally during these

cycles.

The POR will generate the RST signal which will reset the CPU. If any other reset

function is active at the end of this 488 cycle delay, the RST signal will remain in

the reset condition until the other reset condition(s) end.

68HC05CL48 Datasheet(PDF) 43 Page - Motorola, Inc