68HC05CL48 datasheet(69/145 Pages) MOTOROLA

69 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

TIMER

MOTOROLA

REV 2.0

8-17

when the output of the chosen (1 of 4 selection) stage goes active.

1 =

No effect

0 =

Clearing the RTIF

CTOFE - Core Timer Overﬂow Enable

When this bit is set, a CPU interrupt request is generated when the TOF bit is

set, provided the I bit in CCR is cleared.

1 =

Interrupt enable

0 =

Interrupt disable

RTIE - Real Time Interrupt Enable

When this bit is set, a CPU interrupt request is generated when the RTIF bit is

set, provided the I bit in the CCR is cleared.

1 =

Interrupt enable

0 =

Interrupt disable

RT1:RT0 - Rate Select

These two bits select one of four taps from the Real Time Interrupt circuit. The

settings for RTI is listed in Table 8-1. Reset sets these RT0 and RT1, selecting

the lowest periodic rate and therefore the maximum time in which to alter these

bits if necessary.

NOTE

Care should be taken when altering RT0 and RT1 if the time-out

period is imminent or uncertain. If the selected tap is modiﬁed during

a cycle in which the counter is switching, an RTIF could be missed

or an additional one could be generated. To avoid problems, the

COP should be cleared before changing RTI taps.

8.2.3 Ctimer Counter Register (CTCR)

The Core Timer Counter Register is a read-only register which contains the

current value of the 8-bit ripple counter at the beginning of the timer chain. This

counter is clocked at fop divided by 4 and can be used for various functions

including a software input capture. Extended time periods can be attained using

the TOF function to increment a temporary RAM storage location thereby

simulating a 16-bit (or more) counter.

68HC05CL48 Datasheet(PDF) 69 Page - Motorola, Inc

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