68HC05CL48 datasheet(6/145 Pages) MOTOROLA

6 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

MC68HC05CL48

REV 2.0

TABLE OF CONTENTS

Section

Page

10.4.2

ADRC - A/D RC Oscillator Control............................................................. 10-2

10.4.3

ADON - A/D On ......................................................................................... 10-3

10.4.4

CH2:CH0 - Channel Select Bits................................................................. 10-3

10.5

A/D DATA REGISTER (ADDR)...................................................................... 10-3

10.6

A/D DURING WAIT MODE ............................................................................ 10-3

10.7

A/D DURING STOP MODE ........................................................................... 10-4

SECTION 11

CALLER-ID

11.1

FSK DEMODULATOR ................................................................................... 11-2

11.2

CARRIER DETECTOR .................................................................................. 11-2

11.3

RT_L INTERRUPT......................................................................................... 11-2

11.4

RING DETECTOR ......................................................................................... 11-3

11.5

POWER MANAGEMENT............................................................................... 11-4

11.6

DATA INTERFACE ........................................................................................ 11-5

11.7

CALLER-ID REGISTERS............................................................................... 11-6

11.7.1

Control/Status Register1 (CLCSR1) .......................................................... 11-6

11.7.2

Control/Status Register 2 (CLCSR2) ......................................................... 11-7

11.7.3

Control/Status Register 3 (CLCSR3) ......................................................... 11-8

11.7.4

Caller_ID Data Register (CDDR) ............................................................... 11-9

11.8

DESIGN PARAMETERS................................................................................ 11-9

11.9

MESSAGE FORMAT ................................................................................... 11-11

SECTION 12

LCD DRIVER

12.1

LCD RAM. ...................................................................................................... 12-2

12.2

LCD OPERATION.......................................................................................... 12-4

12.3

LCD VOLTAGE GENERATION ..................................................................... 12-7

12.4

LCD CONTROL REGISTER (LCDCR) .......................................................... 12-8

12.5

ELECTRICAL REQUIREMENTS ................................................................... 12-9

12.5.1

DC Requirements ...................................................................................... 12-9

SECTION 13

PHASE-LOCKED LOOP

13.1

PLL CONTROL AND STATUS REGISTER (PCSR $000D) .......................... 13-2

13.2

PLL OPERATIONS ........................................................................................ 13-2

13.3

PLL LOCK TIME ............................................................................................ 13-2

13.4

PLL CLOCK FREQUENCY............................................................................ 13-2

68HC05CL48 Datasheet(PDF) 6 Page - Motorola, Inc

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