68HC05CL48 datasheet(63/145 Pages) MOTOROLA

63 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

TIMER

MOTOROLA

REV 2.0

8-11

Figure 8-5. Timer State Timing Diagram For Input Capture

8.1.4 Timer Control Register (TCR)

The timer control registers TCR is a read/write register. Five bits control interrupts

associated with the timer status register ﬂags IC1F, IC2F, OC1F, OC2F and TOF.

The other two bits control which edge is signiﬁcant to the input capture edge

detector (i.e., negative or positive). The timer control register and the free running

counter are the only sections of the timer affected by reset. The timer control

registers are illustrated below by a deﬁnition of each bit.

76543210

TCR

$0011

READ

IC1IE

IC2IE

OC1IE

OC2IE

TOIE

IEDG2

IEDG1

WRITE

RESET

00000

U = UNAFFECTED

Internal Processor Clock

Internal

Timer

Clocks

T00

T01

T10

T11

Counter (16 bit) $FFEB

$FFEC

$FFED

$FFEE

$FFEF

Input Edge

note

Input Capture Latch

Capture Register

$????

$FFED

Input Capture Flag (ICF)

NOTE: If the input edge occurs in the shaded area from one timer state T10 to the other

timer state T10 the Input Capture Flag is set during the next state T11.

68HC05CL48 Datasheet(PDF) 63 Page - Motorola, Inc

68HC05CL48 Datasheet(HTML) 63 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL