68HC05CL48 datasheet(23/145 Pages) MOTOROLA

23 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

MEMORY

MOTOROLA

REV 2.0

2-1

SECTION 2

MEMORY

The MC68HC05CL48 has a 64k-byte memory map, consisting of user ROM, user

RAM, Self-Check ROM, LCD RAM and I/O as shown in Figure 2-1.

2.1

MEMORY MAP

The MC68HC05CL48 memory map is shown in Figure 2-1.

2.2

I/O AND CONTROL REGISTERS

The I/O and Control Registers reside in locations $0000-$002F. The overall

organization of these registers is shown in Figure 2-1. The bit assignments for

each register are shown in Figure 2-2, Figure 2-3 and Figure 2-4. Reading from

unimplemented bits will return unknown states, and writing to unimplemented bits

will be ignored.

2.2.1 Option Register ($1F)

This register can be written to only once following a Power-On-Reset (POR) but

can be read at any time. This register conﬁgures the MCU options to suit the

user’s application.

OSC_ON

1 =

Oscillator is switched on in STOP mode.

0 =

Oscillator is switched off in STOP mode.

COP

Refer to Section 8 for detailed informations on COP.

1 =

Enable the COP watchdog reset.

0 =

Disable the COP watchdog reset.

76543210

OPT

$001F

READ

OSC_ON

COP

INTO

WRITE

POR

U = UNAFFECTED

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