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68HC05CL48 Datasheet(PDF) 45 Page - Motorola, Inc |
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68HC05CL48 Datasheet(HTML) 45 Page - Motorola, Inc |
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45 / 145 page ![]() June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 LOW POWER MODES MOTOROLA REV 2.0 6-1 SECTION 6 LOW POWER MODES 6.1 LOW-POWER MODES The MC68HC05CL48 has two low-power operational modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP Watchdog Timer is enabled. The flow of the STOP and WAIT modes is shown in Figure 6-1. 6.1.1 STOP Instruction Execution of the STOP instruction, places the MCU in its lowest power consumption mode. In the STOP Mode the internal oscillator is turned off, halting all internal processing, including the COP Watchdog Timer. When the CPU enters STOP Mode, the I-bit in the Condition Code Register will be cleared automatically. This enable the external hardware interrupt to wake up the MCU. All other registers and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the STOP Mode only by a Caller ID (RT_L) interrupt, WTIMER interrupt, a hardware interrupt “IRQ, IRQ(n), KBI(n)” or an externally generated RESET. When exiting the STOP Mode the internal oscillator will resume after a 488 internal processor clock cycle oscillator stabilization delay. 6.1.2 WAIT Instruction The WAIT instruction places the MCU in a low-power mode, which consumes more power than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Other Internal clocks remain active, permitting interrupts to be generated from the functional blocks, or a reset to be generated from the COP Watchdog Timer. The Timer may be used to generate a periodic exit from the WAIT Mode. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any hardware interrupt can wake up the MCU. All other registers, memory, and input/output lines remain in their previous states. |
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