68HC05CL48 datasheet(56/145 Pages) MOTOROLA

56 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

TIMER

MC68HC05CL48

8-4

REV 2.0

counter or counter alternate register ﬁrst addresses the most signiﬁcant byte

(MSB) ($19, $1B), the LSB ($1A, $1C) is transferred to a buffer. This buffer value

remains ﬁxed after the ﬁrst MSB read, even if the user reads the MSB several

times. This buffer is accessed when reading the free-running counter or counter

alternate register LSB ($1A or $1C) and, thus, completes a read sequence of the

total counter value. In reading either the free-running counter or counter alternate

The counter alternate register differs from the counter register in one respect: a

read of the counter register MSB can clear the timer overﬂow ﬂag (TOF).

Therefore, the counter alternate register can be read at any time without the

possibility of missing timer overﬂow interrupts due to clearing of the TOF.

Figure 8-2. Timer State Diagram For Timer Overﬂow

The free-running counter is conﬁgured to $FFFC during reset and is always a

read-only register. During a power-on reset, the counter is also preset to $FFFC

and begins running after the oscillator start-up delay. Because the free-running

counter is 16 bits preceded by a ﬁxed divide-by-four prescaler, the value in the

free-running counter repeats every 262,144 internal bus clock cycles. When the

counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also

be enabled when counter roll over occurs by setting its interrupt enable bit (TOIE).

In some particular timing control applications it may be desirable to reset the 16-

bit free running counter under software control. When the low byte of the counter

($1A or $1C) is written to, the counter is conﬁgured to its reset value ($FFFC).

Internal Processor Clock

Internal

Timer

Clocks

T00

T01

T10

T11

Counter (16 bit)

Timer Overﬂow Flag (TOF)

$FFFE

$FFFF

$0000

$0001

NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is

cleared by read of the Timer Status Register during the internal processor clock time

followed by a read of the counter low register.

$0002

68HC05CL48 Datasheet(PDF) 56 Page - Motorola, Inc

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