PM0214 datasheet(162/245 Pages) STMICROELECTRONICS

162 / 245 page

The STM32 Cortex-M4 instruction set

PM0214

162/245

DocID022708 Rev 4

3.10.18

VMOV ARM Core register to scalar

Transfers one word to a floating-point register from an ARM core register.

Syntax

VMOV{cond}{.32} Dd[x], Rt

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

32 is an optional data size specifier.

•

Dd[x] is the destination, where [x] defines which half of the doubleword is transferred,

as follows:

If x is 0, the lower half is extracted

If x is 1, the upper half is extracted.

•

Rt is the source ARM core register.

Operation

This instruction transfers one word to the upper or lower half of a doubleword floating-point

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

3.10.19

VMRS

Move to ARM Core register from floating-point System Register.

Syntax

VMRS{cond} Rt, FPSCR

VMRS{cond} APSR_nzcv, FPSCR

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

‘Rt’ is the destination ARM core register. This register can be R0-R14.

•

‘APSR_nzcv’ Transfer floating-point flags to the APSR flags.

Operation

This instruction performs one of the following actions:

Copies the value of the FPSCR to a general-purpose register.

Copies the value of the FPSCR flag bits to the APSR N, Z, C, and V flags.

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions optionally change the flags: N, Z, C, V

PM0214 Datasheet(PDF) 162 Page - STMicroelectronics

PM0214 Datasheet(HTML) 162 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL