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C5C5EDELTA-RM/D Datasheet(PDF) 27 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 27 Page - NXP Semiconductors |
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27 / 114 page  03 C5ENPA1-DS/D Rev 03 Chapter 2 SIGNAL DESCRIPTIONS Signal Summary There are ten (10) functional groupings of signals in the C-5e Network Processor: • Clock — 11 pins • Channel Processors (CP0 - CP15) — 16x7 = 112 pins • Executive Processor (XP) — 57 pins – PCI Interface — 50 pins – PROM Interface — 4 pins – Serial Bus Interface — 2 pins – General System Interface — 1 pin • Fabric Processor (FP) — 80 pins • Buffer Management Unit (BMU) — 160 pins • Table Lookup Unit (TLU) — 99 pins • Queue Management Unit (QMU) — 59 pins • Power — 245 pins • Test — 14 pins • No connection (NC) — 3 pins Two (2) of the sections (CPs and FP) are configurable, depending on the type of device being implemented. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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