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C5C5EDELTA-RM/D Datasheet(PDF) 93 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 93 Page - NXP Semiconductors |
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93 / 114 page  AC Timing Specifications 93 03 PROM Interface Timing Specifications The PROM interface timing is shown in Figure 22 and described in Table 51. Figure 22 PROM Interface Timing Diagram SPCK Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 SPDI SPLD SPDO Tspc Tsplo Tspis Tspih Tspdo Table 51 PROM Interface Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tspc SPCK Cycle Time 40.0 ns Tspis SPDI Setup 10.0 ns Tspih SPDI Hold 0.0 ns Tsplo SPLD Output Tsc Tsc + 3.0 ns Tspdo SPDO Output Tsc Tsc + 3.0 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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