C5C5EDELTA-RMSLASHD datasheet(38/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

Gigabit Ethernet and Fibre Channel TBI Configuration

1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same

way as Gigabit Ethernet (GMII). Table 10 shows the possible CP pin combinations you can

use and Figure 4 shows receive and transmit pin configurations by cluster. Table 12 shows

the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.

The unused pins for the two cluster configurations should be wired down using a resistor.

Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 7 1

LVTTL

TCLK

Transmit Clock (125MHz). This clock is used to synchronize the

transmit data.

CPn_1

Table 7 1

CPn_2

Table 7 1

LVTTL

OPD

TXD(9)

Transmit Data (ten bits wide, last on wire)

CPn_3

Table 7 1

LVTTL

TXD(8)

Transmit Data

CPn_4

Table 7 1

LVTTL

TXD(7)

Transmit Data

CPn_5

Table 7 1

LVTTL

OPU

TXD(6)

Transmit Data

CPn_6

Table 7 1

LVTTL

TXD(1)

Transmit Data

CPn+1_0

Table 7 1

CPn+1_1

Table 7 1

ncPU

CPn+1_2

Table 7 1

LVTTL

TXD(5)

Transmit Data

CPn+1_3

Table 7 1

LVTTL

TXD(4)

Transmit Data

CPn+1_4

Table 7 1

LVTTL

OPD

TXD(3)

Transmit Data

CPn+1_5

Table 7 1

LVTTL

TXD(2)

Transmit Data

CPn+1_6

Table 7 1

LVTTL

TXD(0)

Transmit Data (ten bits wide, first on wire)

CPn+2_0

Table 7 1

ncPD

CPn+2_1

Table 7 1

LVTTL

RCLK

Receive Clock (62.5 MHz)

CPn+2_2

Table 7 1

LVTTL

RXD(9)

Receive Data (ten bits wide, last on wire)

CPn+2_3

Table 7 1

LVTTL

IPU

RXD(8)

Receive Data

CPn+2_4

Table 7 1

LVTTL

RXD(7)

Receive Data

CPn+2_5

Table 7 1

LVTTL

RXD(6)

Receive Data

CPn+2_6

Table 7 1

LVTTL

IPU

RXD(1)

Receive Data

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D Datasheet(PDF) 38 Page - NXP Semiconductors

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