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C5C5EDELTA-RM/D Datasheet(PDF) 99 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 99 Page - NXP Semiconductors |
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99 / 114 page  AC Timing Specifications 99 03 QMU SRAM (Internal Mode) Timing Specifications The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and described in Table 57. Figure 26 QMU SRAM (Internal Mode) Timing Diagram Data (TDn) TD0 - TD63, TPAR0-3 Table 56 Signal Groups in TLU Timing Diagrams SIGNAL GROUP INCLUDED SIGNALS QACLKI Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Q_ctl QAn QDn (output) QDn (input) Tqc Tqdo Tqco Tqao Tqdv Tqds Tqdz Tqdh Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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