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C5C5EDELTA-RM/D Datasheet(PDF) 102 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 114 page  102 CHAPTER 3: ELECTRICAL SPECIFICATIONS C Table 59 QMU to Q-5 (External Mode) Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tqec QMU External Cycle Time 10.0 ns QACLKO/QBCLKO derived from QACLKI/QBCLKI Tqep QMU CLKA-CLKB delta between rising edges 4.8 ns Tqes QMU Input Data Setup 0.6 ns Tqeh QMU Input Data Hold 0.8 ns Tqeo QMU Data Output -.85 1.3 ns Determines valid time for data from each clock rising edge Table 60 Signal Groups in QMU to Q-5 (External Mode) Timimg Diagrams SIGNAL GROUP INCLUDED SIGNALS Input Clocks (QnCLKI) QACLKI, QBCLKI Output Clocks (QnCLKO) QACLKO, QBCLKO Input Data (DQDATA) QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR Output Data (NQDATA) QA0-16, QWEX, QD24-31 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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