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C5C5EDELTA-RM/D Datasheet(PDF) 83 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 83 Page - NXP Semiconductors |
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83 / 114 page  AC Timing Specifications 83 03 CP Timing Specifications This section describes the timing for the following CP interfaces: • DS1/DS3 • 10/100 Ethernet • Gigabit Ethernet • OC-3 • OC-12 DS1/DS3 Timing Specifications The DS1/DS3 interface timing is shown in Figure 14 and described in Table 42. Figure 14 DS1/DS3 Ethernet Timing Diagram † The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5e NP. It is also possible to use one or more CCLKn inputs for other frequencies; contact your Motorola representative for more information. CPn_0 (TCLK) Cycle 1 Cycle 2 Cycle 2 Cycle 3 Cycle 3 Cycle 4 Cycle 4 Cycle 5 Cycle 5 CPn_2/3 (Tx) CPn_1 (RCLK) CPn_4/5 (Rx) Tcdt Tcdo Tcdr Tcds Tcdh Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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