C5C5EDELTA-RMSLASHD datasheet(36/114 Pages) NXP

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CHAPTER 2: SIGNAL DESCRIPTIONS

Figure 4 GMII/TBI Transmit and Receive Pin Configurations

Cluster

Port 1

Port 2

Port 3

Port 4

}

Single Cluster Mode

Pin Configuration

Port 1

Port 2

}

Two Cluster Mode

Pin Configuration

}

nc = not connected

Cluster

Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example

SIGNAL NAME*

PIN #†

TOTAL

TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 7 1

LVTTL

T_CLK

GMII Transmit Clock (125MHz). This clock is used to synchronize the

transmit data.

CPn_1

Table 7 1

LVTTL

TCLKI

MII transmit clock. Transmit data aligned to this clock input from

phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT

CPn_2

Table 7 1

LVTTL

TXD(0)

Transmit Data (byte-wide data, least significant bit)

CPn_3

Table 7 1

LVTTL

TXD(1)

Transmit Data

CPn_4

Table 7 1

LVTTL

TXD(2)

Transmit Data

CPn_5

Table 7 1

LVTTL

TXD(3)

Transmit Data

CPn_6

Table 7 1

LVTTL

TX_EN

Transmit Enable. When asserted, the data on TXD is encoded and

transmitted on the twisted pair cable.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D Datasheet(PDF) 36 Page - NXP Semiconductors

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