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C5C5EDELTA-RM/D Datasheet(PDF) 90 Page - NXP Semiconductors |
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C5C5EDELTA-RM/D Datasheet(HTML) 90 Page - NXP Semiconductors |
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90 / 114 page ![]() 90 CHAPTER 3: ELECTRICAL SPECIFICATIONS C Table 48 PCI Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tpc PCI Cycle Time* * 66MHz PCI 15.0 ns Tpas PAD/P_ctl† Setup † P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX 3.0 ns Tpah PAD/P_ctl Hold 0.0 ns Tpao PAD/P_ctl Output 2.0 6.0 ns Tpaz PAD/P_ctl Clk to Tri‡ ‡ Not fully tested, values based on design/characterization. 2.0 6.0 ns Tpav PAD/P_ctl Clk to Driven‡ 2.0 6.0 ns Tpgs PGNTX Setup 5.1 ns Tpgh PGNTX Hold 0.0 ns Tpis PIDSEL Setup 3.0 ns Tpih PIDSEL Hold 0.0 ns PRSTX** ** Asynchronous ns PINTA** ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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