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C5C5EDELTA-RM/D Datasheet(PDF) 56 Page - NXP Semiconductors

Part # C5C5EDELTA-RM/D
Description  C-5e NETWORK PROCESSOR SILICON REVISION A1
PDF  114 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

C5C5EDELTA-RM/D Datasheet(HTML) 56 Page - NXP Semiconductors

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56
CHAPTER 2: SIGNAL DESCRIPTIONS
C
QMU to Q-5 TMC (External
Mode) Interface Signals
The QMU to Q-5 Traffic Management Coprocessor (TMC) signals are described in Table 28.
Table 28 QMU to Q-5 (External Mode) Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
QA0 - QA15
C8, B8, A8, F9, E9, D9, C9, B9, A9, F10, D10,
C10, A10, G11, F11, E11
16
LVTTL
O
Enqueue Data [8:23]
QA16
D11
1
LVTTL
O
Enqueue Parity
QD0 - QD23
G1, F1, E1, D1, C1, B1, G2, F2, D2, C2, A2, G3,
E3, D3, B3, A3, G4, F4, E4, D4, C4, B4, A4, G5
24
LVTTL
I
PD
Dequeue Data [0:23]
QD24 - QD31
F5, E5, D5, C5, B5, A5, F6, D6
8
LVTTL
I
PD
Enqueue Data [0:7]
QDQPAR
C11
1
LVTTL
I
PD
Dequeue Parity
QARDY
E8
1
LVTTL
I
PD
Dequeue Ack Ready
QNQRDY
D8
1
LVTTL
I
PD
Enqueue Ready
QWEX
C6
1
LVTTL
O
Dequeue Ready
QBCLKO
A6
1
LVTTL
O
Output ClockB
QBCLKI
E7
1
LVTTL
I
PD
Input ClockB
QACLKO
D7
1
LVTTL
O
Output ClockA
QACLKI
B7
1
LVTTL
I
PD
Input ClockA
QDPL
A7
1
LVTTL
O
Dequeue Ack [0]
QDPH
F8
1
LVTTL
O
Dequeue Ack [1]
TOTAL PINS
59
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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