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TJA1080ATS/2/T Datasheet(PDF) 20 Page - NXP Semiconductors |
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TJA1080ATS/2/T Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 49 page ![]() TJA1080A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 24 February 2011 20 of 49 NXP Semiconductors TJA1080A FlexRay transceiver 6.5 Wake-up mechanism 6.5.1 Node configuration In Sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Standby mode or Go-to-sleep mode (depending on the value at pin EN), if the wake flag is set. Consequently, pins INH1 and INH2 are switched on. If no undervoltage is present on pins VIO and VBAT, the transceiver switches immediately to the mode indicated on pins EN and STBN. In Standby, Go-to-sleep and Sleep modes pins RXD and RXEN are driven LOW if the wake flag is set. 6.5.2 Star configuration In Star-sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Star-idle mode (pins INH1 and INH2 are switched on) if the wake flag is set. After entering Star-idle mode the transceiver monitors for activity to choose the appropriate mode transition (see Figure 6). 6.5.3 Remote wake-up 6.5.3.1 Bus wake-up via wake-up pattern Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated by an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least tdet(wake)idle are present on the bus lines within tdet(wake)tot. 6.5.3.2 Bus wake-up via dedicated FlexRay data frame The reception of a dedicated data frame, emulating a valid wake-up pattern, as shown in Figure 9, sets the wake-up flag of the TJA1080A. Due to the Byte Start Sequence (BSS), preceding each byte, the DATA_0 and DATA_1 phases for the wake-up symbol are interrupted every 1 μs. For 10 Mbit/s the maximum interruption time is 130 ns. Such interruptions do not prevent the transceiver from recognizing the wake-up pattern in the payload of a data frame. The wake-up flag will not be set upon reception of an invalid wake-up pattern. Fig 8. Bus wake-up timing 001aae442 0 V −425 mV Vdif tdet(wake)tot tdet(wake)Data_0 tdet(wake)idle tdet(wake)Data_0 tdet(wake)idle |
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