TJA1080ATSSLASH2SLASHT datasheet(7/49 Pages) NXP

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TJA1080A

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Product data sheet

Rev. 5 — 24 February 2011

7 of 49

NXP Semiconductors

TJA1080A

FlexRay transceiver

6.1.3 Bus activity and idle detection

The following mechanisms for activity and idle detection are valid for node and star

configurations in normal power modes:

• If the absolute differential voltage on the bus lines is higher than |Vi(dif)det(act)| for

tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to

LOW which results in pin RXD being released:

– If, after bus activity detection, the differential voltage on the bus lines is higher than

VIH(dif), pin RXD will go HIGH

– If, after bus activity detection, the differential voltage on the bus lines is lower than

VIL(dif), pin RXD will go LOW

• If the absolute differential voltage on the bus lines is lower than |Vi(dif)det(act)| for

tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH.

This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)

Additionally, in star configuration, activity and idle can be detected (see Figure 6 for state

transitions due to activity/idle detection in star configuration):

• If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN

• If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN

• If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on

pins TRXD0 and TRXD1

• If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on

pins TRXD0 and TRXD1

6.2 Operating modes in node configuration

The TJA1080A provides two control pins STBN and EN in order to select one of the

modes of operation in node configuration. See Table 3 for a detailed description of the pin

signalling in node configuration, and Figure 3 for the timing diagram.

All modes are directly controlled via pins EN and STBN unless an undervoltage situation

is present.

If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates the status of

the error flag.

[1]

Pin ERRN provides a serial interface for retrieving diagnostic information.

[2]

Valid if VIO and (VBUF or VBAT) are present.

[3]

If wake flag is not set.

Table 3.

Pin signalling in node configuration

Mode

STBN EN

ERRN[1]

RXEN

RXD

Transmitter INH1

INH2

LOW

HIGH

LOW

HIGH

LOW

HIGH

Normal

HIGH

HIGH error flag

set

error flag

reset

bus

activity

bus

idle

bus

DATA_0

bus

DATA_1

or idle

enabled

HIGH HIGH

Receive-only

HIGH

LOW

disabled

Go-to-sleep

LOW

HIGH error flag

set[2]

error flag

reset

wake flag

set[2]

wake

flag

reset

wake flag

set[2]

wake

flag

reset

float[3]

Standby

LOW

Sleep

LOW

float

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