IMX28AEC datasheet(35/72 Pages) FREESCALE

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i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1

Freescale Semiconductor

Figure 10 shows MII transmit signal timings. Table 40 describes the timing parameters (M5–M8) shown

in the figure.

Figure 10. MII Transmit Signal Timing Diagram

1 ENET0_TX_EN, ENET0_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

3.5.4.1.3

MII Asynchronous Inputs Signal Timing (ENET0_CRS and ENET0_COL)

Figure 11 shows MII asynchronous input timings. Table 41 describes the timing parameter (M9) shown in

the figure.

Figure 11. MII Async Inputs Timing Diagram

1 ENET0_COL has the same timing in 10-Mbit 7-wire interface mode.

Table 40. MII Transmit Signal Timing

Characteristic1

Min.

Max.

Unit

ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN,

ENET0_TX_ER invalid

5—

ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN,

ENET0_TX_ER valid

—20

ENET0_TX_CLK pulse width high

35%

65%

ENET0_TX_CLK

period

ENET0_TX_CLK pulse width low

35%

65%

ENET0_TX_CLK

period

Table 41. MII Asynchronous Inputs Signal Timing

Characteristic

Min.

Max.

Unit

M91

ENET0_CRS to ENET0_COL minimum pulse width

1.5

—

ENET0_TX_CLK period

ENET0_TX_CLK (input)

ENET0_TXD[3:0] (outputs)

ENET0_TX_EN

ENET0_TX_ER

ENET0_CRS, ENET0_COL

IMX28AEC Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

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