IMX28AEC datasheet(57/72 Pages) FREESCALE

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i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1

Freescale Semiconductor

3.5.14.4

SPI AC Timing

Figure 41 depicts the master mode and slave mode timings of the SPI, and Table 62 lists the timing

parameters.

Figure 41. SPI Interface Timing Diagram

MS4

SCK Rise Time

tCLKr

—

MS5

SCK Fall Time

tCLKf

—

MS11

BS Setup Time

tBSsu

—

MS12

BS Hold Time

tBSh

—

MS13

DATA Setup Time

tDsu

—

MS14

DATA Hold Time

tDh

—

MS15

DATA Input Delay Time

tDd

—

Table 62. SPI Interface Timing Parameters

Parameter

Symbol

Min.

Max.

Units

CS1

SCK cycle time

tclk

—

CS2

SCK high or low time

tSW

—

CS3

SCK rise or fall

tRISE/FALL

—7.6

CS4

SSn pulse width

tCSLH

—

CS5

SSn lead time (CS setup time)

tSCS

—

CS6

SSn lag time (CS hold time)

tHCS

—

CS7

MOSI setup time

tSmosi

5—

CS8

MOSI hold time

tHmosi

5—

CS9

MISO setup time

tSmiso

5—

CS10

MISO hold time

tHmiso

5—

Table 61. MS Parallel Transfer Timing Parameters (continued)

Parameter

Symbol

Min

Max

Units

CS7

CS8

CS2

CS4

CS6

CS9

CS10

SCK

SSn

MISO

MOSI

CS1

CS3

CS5

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