IMX28AEC datasheet(7/72 Pages) FREESCALE

7 / 72 page

i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1

Freescale Semiconductor

DFLPT

Default

first-level page

table

System control

The DFLPT provides a unique method of implementing the ARM MMU

first-level page table (L1PT) using a hardware-based approach.

DIGCTL

Digital control

and on-chip

RAM

System control

The digital control module includes sections for controlling the SRAM, the

performance monitors, high-entropy pseudo-random number seed,

free-running microseconds counter, and other chip control functions.

DUART

Debug UART

Connectivity

peripherals

The Debug UART performs the following data conversions:

• Serial-to-parallel conversion on data received from a peripheral device

• Parallel-to-serial conversion on data transmitted to the peripheral device

EMI

External

memory

interface

Connectivity

peripherals

The i.MX28 supports off-chip DRAM storage through the EMI controller,

which is connected to the four internal AHB/AXI busses. The EMI supports

multiple external memory types, including:

• 1.8-V Mobile DDR1 (LP-DDR1)

• Standard 1.8-V DDR2

• Low Voltage 1.5-V DDR2 (LV-DDR2)

ENET

Ethernet MAC

Controller

Connectivity

peripherals

Ethernet MAC controller connected to the uDMA (unified DMA). Supports

10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also

supports RMII or MII connectivity.

FlexCAN(2)

Controller

area network

module

Connectivity

peripherals

The Controller Area Network (CAN) protocol is a message based protocol

used for serial data. It was designed specifically for automotive but is also

used in industrial control and medical applications. The serial data bus runs

at 1 Mbps.

GPMI

General-pur-

pose media

interface

Connectivity

peripherals

The General-Purpose Media Interface (GPMI) controller is a flexible NAND

flash controller with 8-bit data width, up to 50-MBps I/O speed and individual

chip select and DMA channels for up to 8 NAND devices. It also provides a

interface to 20-bit BCH for ECC.

HSADC

High-speed

ADC

Connectivity

peripherals

The high-speed ADC block is designed to sample an analog input with 12-bit

resolution and a sample rate of up to 2 Msps. The output of the HSADC block

can be moved to the external memory through APBH-DMA. A typical user

case of the HSADC is to work with the PWM block to drive an external linear

image scanner sensor.

I2C(2)

I2C module

Connectivity

peripherals

The I2C is a standard two-wire serial interface used to connect the chip with

peripherals or host controllers. The I2C operates up to 400 kbps in either I2C

master or I2C slave mode. Each I2C has a dedicated DMA channel and can

also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and

10-bit device address in master mode, and has programmable 7-bit address

in slave mode.

ICOLL

Interrupt

Collector

System control

The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt

collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or

IRQ line of the ARM9 CPU.

L2 Switch

3-Port L2

Switch

Network Control Programmable 3-Port Ethernet Switch with QOS

Table 4. i.MX28 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

IMX28AEC Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

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