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IMX28AEC Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc |
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IMX28AEC Datasheet(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 72 page ![]() i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1 Freescale Semiconductor 37 Figure 13 shows RMII mode timings. Table 43 describes the timing parameters (M16–M21) shown in the figure. Figure 13. RMII Mode Signal Timing Diagram 3.5.5 Coresight ETM9 AC Interface Timing The following timing specifications are given as a guide for a TPA that supports TRACECLK frequencies up to 80 MHz. 3.5.5.1 TRACECLK Timing This section describes TRACECLK timings. Table 43. RMII Signal Timing ID Characteristic Min. Max. Unit M16 ENET_CLK pulse width high 35% 65% ENET_CLK period M17 ENET_CLK pulse width low 35% 65% ENET_CLK period M18 ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN invalid 3 — ns M19 ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN valid — 12 ns M20 ENET0_RXD[1:0], CRS_DV(ENET0_RX_DV), ENET0_RX_ER to ENET_CLK setup 2— ns M21 ENET_CLK to ENET0_RXD[1:0], ENET0_RX_DV, ENET0_RX_ER hold 2 — ns ENET_CLK (input) ENET0_TX_EN M16 M17 M18 M19 M20 M21 ENET0_RXD[1:0] ENET0_TXD[1:0] (output) ENET0_RX_ER CRS_DV (input) |
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